1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device, and more particularly to a MOS random-access memory employing one-transistor memory cells arranged in rows and columns.
2. Description of the Related Art
MOS random access memory (RAM) devices have become more widely used in the manufacture of digital equipment as the speed of these devices increases while their cost decreases. The cost of a storage using MOS RAMs per bit has gone down as the number of bits per package or the number of memory cells has gone up. Recently, as the performance of digital equipment is improved, enhancement of the data accessing speed for such MOS RAM is demanded more severely.
To fulfill such a demand, presently-available dynamic RAMs (DRAMs) are provided with a high-speed access mode, such as page mode, nibble mode or static-column mode, in addition to the normal access mode. In the field of digital image-processing or computer systems designed to improve the data exchange with external storage units using a cache memory, it is also demanded strongly to realize a so-called "serial access" mode. The serial access mode is to serially access one selected row of memory cells and output the accessed results in a fixed order.
However, none of the above modes conventionally established are satisfactory. This is because these modes cannot sufficiently satisfy today's demand concerning high-speed data access in highly advanced digital equipment for the following reasons.
In the conventional page mode, those of memory cells of a DRAM which are associated with a selected row line can be accessed serially. Externally giving serial addresses can permit serial access to the selected row of memory cells. The improvement of the serial accessing speed is however still limited, which depends on the necessity to externally fetch individual column addresses every time in accordance with potential toggles of a column address-strobe signal (CAS). This is an impediment hard to overcome for DRAMs that operate in page mode.
In a nibble mode, serial data access, such as read and write operations, is performed on a designated column in response to the toggles of CAS. The nibble mode is similar to the page mode in that the access operation is controlled only by the toggles of CAS. The nibble mode is however superior to the page mode in accessing speed. This arises because the nibble mode does not require to fetch the column address for each bit access operation after the second CAS cycle.
The nibble mode suffers from the limitation of the number of bits or memory cells which can be designed accessible at a time. The limitation of the accessible bit data number is originated from the following circumstances. In nibble mode multiple pieces of bit data are simultaneously transferred to a data latch register in the first toggling cycle of CAS. In response to the subsequent toggles of CAS, proper pieces of the latched pieces of bit data are selected at random and are sequentially transferred to an output port. Here, the number of registers provided in the data latch register determines the number of accessible bits. The number of the registers is not permitted to freely increase due to the limitation of the area on the chip substrate of the DRAM (the limitation of the layout margin); this number is set as high as about four bits. The limitation of the maximum accessible bit data number significantly clouds the aforementioned merit of the nibble mode.
It has been tried to apply the nibble mode to a serial accessing operation in order to provide high-speed serial access. In this case after multiple pieces of data stored in a column of memory cells are transferred to a data-latch register by activating one column address-select line, the sense operation gets started in the data-latch register. The number of selected cells is called "bit length," which corresponds to the maximum accessible data-bit number in nibble mode.
To achieve the serial access, a column address counter is typically mounted on the DRAM chip. The column address counter sequentially increases the internal address. It is necessary to activate a sense-activation signal QSE in the data latch register each time for specific CAS cycles (4n+1 CAS cycles when the accessible bit number is "4" where n=1, 2, . . . ). That is, the access time is delayed before 4n+1 CAS cycles come. The delayed sense time is twice as long as or longer than the ordinary sense time. The delay of sense time inevitably occurs in a specific time interval; this is a bottleneck in improving the total access speed of DRAMs.